Field Effect Semiconductor Diodes and Processing Techniques

ABSTRACT

Field effect semiconductor diodes and improved processing techniques for forming the field effect semiconductor diodes having semiconductor layers forming a source, a body and a drain of a field effect device, the semiconductor layers forming pedestals having an insulating layer and a gate on sides thereof vertically spanning the body and a part of the source and drain layers, and a conductive contact layer over the pedestals making electrical contact with the drain and the gate, the conductive layer being in contact with the body at least one position on each pedestal. The conductive layer may be in contact with the body through at least one opening in the source layer, or the source layer may be a discontinuous doped layer, the body layer extending between the discontinuous doped layer forming the source layer to be in electrical contact with the conductive layer. Other aspects and variations of the invention are disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional PatentApplication No. 60/785,306 filed Mar. 23, 2006 and U.S. ProvisionalPatent Application No. 60/785,307 filed Mar. 23, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor devices andfabrication of the same. The present invention more particularly relatesto semiconductor diodes and their methods of fabrication.

2. Prior Art

Reference is made to prior art U.S. Pat. No. 6,537,921, the disclosureof which is hereby incorporated by reference. Semiconductor devices ofvarious kinds are well known in the prior art. Because the presentinvention relates to semiconductor diodes and how they are fabricated,the focus of this section will be semiconductor diodes.

Semiconductor diodes are widely used in electronic circuits for variouspurposes. The primary purpose of such semiconductor diodes is to provideconduction of current in a forward direction in response to a forwardvoltage bias, and to block conduction of current in the reversedirection in response to a reverse voltage bias. This rectifyingfunction is widely used in such circuits as power supplies of variouskinds as well as in many other electronic circuits.

In typical semiconductor diodes, conduction in the forward direction islimited to leakage current values until the forward voltage bias reachesa characteristic value for the particular type of semiconductor device.By way of example, silicon pn junction diodes don't conductsignificantly until the forward bias voltage is at least approximately0.7 volts. Many silicon Schottky diodes, because of the characteristicsof the Schottky barrier, can begin to conduct at lower voltages, such as0.4 volts. Germanium pn junction diodes have a forward conductionvoltage drop of approximately 0.3 volts at room temperature. However,the same are currently only rarely used, not only because of theirincompatibility with silicon integrated circuit fabrication, but alsoeven as a discrete device because of temperature sensitivity and otherundesirable characteristics thereof.

In some applications, diodes are used not for their rectifyingcharacteristics, but rather to be always forward biased so as to providetheir characteristic forward conduction voltage drop. For instance, inintegrated circuits, diodes or diode connected transistors arefrequently used to provide a forward conduction voltage dropsubstantially equal to the base-emitter voltage of another transistor inthe circuit. While certain embodiments of the present invention may finduse in circuits of this general kind, such use is not a primaryobjective thereof.

In circuits, which utilize the true rectifying characteristics ofsemiconductor diodes, the forward conduction voltage drop of the diodeis usually a substantial disadvantage. By way of specific example, in aDC to DC step-down converter, a transformer is typically used wherein asemiconductor switch controlled by an appropriate controller is used toperiodically connect and disconnect the primary of the transformer witha DC power source. The secondary voltage is connected to a converteroutput, either through a diode for its rectifying characteristics, orthrough another semiconductor switch. The controller varies either theduty cycle or the frequency of the primary connection to the powersource as required to maintain the desired output voltage. If asemiconductor switch is used to connect the secondary to the output, thecontroller also controls the operation of this second switch.

Use of a semiconductor switch to couple the secondary to the output hasthe advantage of a very low forward conduction voltage drop, though hasthe disadvantage of requiring careful control throughout the operatingtemperature range of the converter to maintain the efficiency of theenergy transfer from primary to secondary. The use of a semiconductordiode for this purpose has the advantage of eliminating the need forcontrol of a secondary switch, but has the disadvantage of imposing theforward conduction voltage drop of the semiconductor diode on thesecondary circuit. This has at least two very substantial disadvantages.First, the forward conduction voltage drop of the semiconductor diodedevice can substantially reduce the efficiency of the converter. Forinstance, newer integrated circuits commonly used in computer systemsare designed to operate using lower power supply voltages, such as 3.3volts, 3 volts and 2.7 volts. In the case of a 3 volt power supply, theimposition of a 0.7 volt series voltage drop means that the converter isin effect operating into a 3.7 volt load, thereby limiting theefficiency of the converter to 81%, even before other circuit losses areconsidered.

Second, the efficiency loss described above represents a power loss inthe diode, resulting in the heating thereof. This limits the powerconversion capability of an integrated circuit converter, and in manyapplications requires the use of a discrete diode of adequate size,increasing the overall circuit size and cost.

Another commonly used circuit for AC to DC conversion is the full wavebridge rectifier usually coupled to the secondary winding of atransformer having the primary thereof driven by the AC power source.Here two diode voltage drops are imposed on the peak DC output, makingthe circuit particularly inefficient using conventional diodes, andincreasing the heat generation of the circuit requiring dissipationthrough large discrete devices, heat dissipating structures, etc.depending on the DC power to be provided.

Therefore, it would be highly advantageous to have a semiconductor diodehaving a low forward conduction voltage drop for use as a rectifyingelement in circuits wherein the diode will be subjected to both forwardand reverse bias voltages from time to time. While such a diode may findmany applications in discrete form, it would be further desirable forsuch a diode to be compatible with integrated circuit fabricationtechniques so that the same could be realized in integrated circuit formas part of a much larger integrated circuit. Further, while reversecurrent leakage is always undesirable and normally must be made up byadditional forward conduction current, thereby decreasing circuitefficiency, reverse current leakage can have other and more substantialdeleterious affects on some circuits. Accordingly it would also bedesirable for such a semiconductor diode to further have a low reversebias leakage current.

In many applications it is required that the diode be put across a coilsuch as a transformer. In these instances it is possible for a reversevoltage to be applied to the diode of sufficient magnitude to force itinto reverse breakdown, specifically into a junction avalanchecondition. This is particularly true in DC to DC converters which use arapidly changing waveform to drive transformer coils which are connectedacross diode bridges. In these applications a specification requirementfor “Avalanche Energy” capability is a parameter normally included inthe data sheets. The avalanche energy capability of a diode is asignificant factor for a designer of such circuits. The avalanche energycapability determines how much design margin a designer has whendesigning a semiconductor diode into a circuit. The larger the number ofavalanche energy capability the more design flexibility a circuitdesigner has.

The avalanche energy capability is a measure of the diode's capabilityto absorb the energy from the coil, where energy E=(½)*I²*L, withoutdestroying the diode. These requirements are typically on the order oftens of millijoules. A key factor in the ability of a diode tonondestructively dissipate this energy is the amount of junction areathat dissipates the energy i.e., the area of the junction that actuallyconducts during avalanche. High avalanche energy capability of asemiconductor diode improves its utilization.

At the same time, it is desirable to lower the costs of semiconductordiodes by reducing their size and by improving their methods offabrication.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of a prior art diode of the type of interestherein taken on a plane through the pedestals perpendicular to theusually elongate pedestals.

FIG. 2 is a cross section of a preferred embodiment of the presentinvention taken on the same plane as FIG. 1.

FIG. 3A is a cross section of an alternate embodiment taken on the sameplane as FIG. 1, together with a cross section taken along lines A-A,both illustrating an alternative technique of forming backgate contacts.

FIG. 3B is a cross section of a second alternate embodiment taken on thesame plane as FIG. 1, together with a cross section taken along linesA-A, both illustrating a second alternative technique of formingbackgate contacts.

FIG. 3C is a cross section illustrating a third alternative technique offorming backgate contacts.

FIG. 4A is a cross section illustrating a preferred embodiment utilizingan implanted anode region with a photoresist mask to form the backgatecontact regions.

FIG. 4A1 is a cross section taken along line 4A1-4A1 of FIG. 4Aillustrating a diode before the anode has been driven to its finaldepth.

FIG. 4B is a top view illustrating the formation of pedestals for theFET devices of the present invention.

FIG. 4B1 is a cross section taken alone line 4B1-4B1 of FIG. 4B.

FIG. 4C is a cross section illustrating the implantation of thethreshold adjustment.

FIG. 4D is a cross section illustrating the formation of the FET gate.

FIG. 4E is a cross section illustrating the metallization resulting inthe final device profile.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The diodes of interest in the present invention are FET structures, asshown in prior art cross section, FIG. 1, with a common gate 160 andanode 130. These also have the FET body (backgate) 140 common to theanode and gate. For the discussion of these devices we will assume theuse of an N-Channel FET. Similar discussions with P-Channel FETs wouldrequire the exchange of material conductivity types and anode/cathodeterms. For completeness, 100 is the wafer substrate, 105 is theN-epitaxial region, 110 is the breakdown voltage enhancement implantregion, 120 is the device anode metallization, 150 is the gatedielectric material and 170 is the cathode enhancement diffusion.

A cross section of the preferred embodiment of the present invention ispresented in FIG. 2. The major differences from the prior art areelimination of the cathode enhancement diffusion 170, and extension ofthe anode diffusion 130 to the top surface. The elimination of diffusion170 is discussed in the prior art patent hereinbefore referred to, butis included here for completeness to illustrate the alternativeembodiment. Also note the specific identification of the backgatecontact 145, connecting the backgate 140 to the anode metallization 120.Although the term metallization is used here, it also applies to anyconductive interconnect layer which may be used to connect theelectrodes such as silicide, or polysilicon. This backgate structure isformed by masking the anode implant using an oxide mask, or photoresist.The pedestals, whose cross sections are shown in the Figures, can beislands of any desired shape on top surface of the substrate, such assmall circular mesas, rectangular mesas, or any desired shape ofcylindrical cylinder with a height as shown in the cross section. Theymay also be long narrow rectangles of width approximately 0.6 micronsand lengths extending the entire width or length of the die referred toas long fingers. The preferred form is long fingers.

Due to the low current required for the backgate functionality, thebackgate contact may consist of isolated contacts along the length ofthe fingers, typically one every 20 um for a finger approximately 0.6 umwide, rather than continuous connection along the length of the fingersas shown in FIG. 2. The substrate may also be an insulator such as inSOI construction with an added contact (not shown) to access thecathode.

FIG. 3A presents an alternative technique of forming these contacts. Inthis embodiment, the anode 130 is formed as a separate epitaxial layer,and then etched away to expose the backgate 140 and form backgatecontacts 145. In lieu of growing an epitaxial layer, the anode layer maybe formed by a blanket ion implantation followed by a drive. The drivemay be later in the process and serve other purposes, for example thedamage anneal after a silicon trench etch.

FIG. 3B presents a second alternative backgate contact by utilizing aphotoresist or oxide mask to block the anode implant which after thermaltreatment results in the indicated anode structure 130. This techniqueis somewhat simplified in comparison to the embodiment of FIG. 3Abecause it does not leave a step in the silicon; and is simplified incomparison to the prior art hereinbefore referred to because it does notrequire the separate initial trench etch required in that embodiment;however, it does require more thermal treatment, and possible shiftingof diffusions which must be taken into account.

A third alternative embodiment is presented in FIG. 3C. In thisembodiment, the oxide masking level is cut with an initial mask, usedfor alignment target cuts; however, since this cuts the alignmenttargets cut into the silicon, it results in a vertical oxide step at thebackgate contact 145. There is still an oxide mask over region 145during the anode implant which keeps the implant 130 out of the contactregion. Again FIG. 3B is preferred because of the planar surface thatresults. The step at 145 will be imaged during the trench etches whichmay have an impact on device performance, unless critical mask alignmentis used for the trench etch steps so that the contacts are localized tothe top of the pedestals only.

It is clear that, with the various options for forming the backgatecontact, there is much flexibility in the sequence of forming theoverall device structure. These contacts may be formed early in theprocess, before any substantial wafer processing has occurred, or laterafter the trenches have been cut. Again, for illustrative purposes, anN-Channel device will be assumed with the understanding that P-Channeldevices can also be constructed by switching material types andelectrode names.

For the embodiment of choice, the process begins with a low resistivitysubstrate, less than 0.002 Ohm-Cm. An N-buffer layer is epitaxiallygrown on top of this to support the reverse breakdown voltage, followedby a p-type epitaxial region where the device channel will be formed.The preferred embodiment utilizes an implanted anode region 130 with aphotoresist mask to form the back contact regions 145 by selectivelyblocking the implant shown in top view FIG. 4A, thus leaving the p-typebackgate exposed at the surface of the silicon. This results in thecross section presented in FIG. 4A1, where the anode has not yet beendriven to its final depth. The anode concentration is relatively high,typically 10²⁰/cc, to facilitate ohmic contact to metallization in alater step.

FIG. 4B presents a top view of the next step, in which trenches are cutinto the silicon, through layers 130 and 140 exposing N-Type epitaxiallayer 105 (cathode), to form the pedestals 135 for the FET devices.These trenches are approximately perpendicular to the contact masking asshown in FIG. 4B, although the alignment to this masking step is notcritical, ±30° is acceptable. A cross section after this step ispresented in FIG. 4B1. This typically is followed by an annealingprocess to remove any residual etch damage, and to drive the anodeslightly deeper. It will be noted that the trench etch extends below thebackgate silicon 140 to provide a surface for the FET gate construction.FIG. 4B also presents the relationship among the substrate 100, theN-epitaxial layer 105 (cathode), the backgate region 140, and theimplanted anode 130 at the end of these steps. It is understood that theintermediate steps of forming and patterning the oxide mask necessaryfor the trench etch, which are presented in the referenced patent, areincluded here by that reference.

FIG. 4C presents the next step where the threshold adjustment 180 isimplanted into the side walls at an angle, typically 15° from thevertical on each of the two pedestal walls. This may be done through asacrificial oxide as is usual in the industry to provide some additionalresistance to implant channeling. After striping the sacrificial oxide,if used, a gate oxidation step follows, and the application of gateelectrode material to the pedestal wall forms the FET gate 190, FIG. 4D.Heavily doped poly silicon is normally used for this electrode material.The polysilicon is heavily doped to control the work function, andetched away from the bottom of the trench and the top of the pedestal.An additional trench etch is performed to remove the residual thresholdadjust implant from the bottom of the trench; and recesses the poly fromthe top of the pedestal. This processing results in the sectionpresented in FIG. 4D.

An additional P-type implant 110 follows, to provide electricalisolation in the trench bottom, and to enhance the reverse bias voltagebreakdown characteristics of the device. Following this implant athermal process is used to electrically activate the various dopants,after which the metallization 120 is applied resulting in the finaldevice profile, FIG. 4E.

In the exemplary N-channel field effect device, the anode is the drainand the cathode is the source. In that regard, the source and drainlabels, as used herein and in the claims to follow, refer to the sourceas being that region (105 or 130) that is the source of the chargecarriers when the diode is turned on or conducting, and with the drainbeing the other region (130 or 105) of the same conductivity type.Therefore, the charge carriers flow from the source through the channelto the drain during conduction. In the case of the exemplary N-typedevices disclosed herein, conduction occurs when the drain 130 (anode)is at a higher voltage than the source 105 (cathode). With the foregoingdefinition of source and drain, it will be noted that regardless of theconductivity type, the backgate 140 is connected to the drain, not thesource. This is to be compared to a conventional integrated circuitstructure wherein the backgate is connected to the source.

According to the foregoing, region 105 has been identified as thesource, independent of the conductivity type. As alternate embodimentsto enhance the breakdown voltage, region 105 may be a drift region, inwhich case region 100 would be the source.

While certain preferred embodiments of the present invention have beendisclosed and described herein for purposes of illustration and not forpurposes of limitation, it will be understood by those skilled in theart that various changes in form and detail may be made therein withoutdeparting from the spirit and scope of the invention.

1-20. (canceled)
 21. A method of forming a field effect semiconductordiode, where the diode comprises semiconductor layers on an uppersurface of a substrate and forming a source, a body and a drain of afield effect device, the semiconductor layers being stacked verticallyand forming pedestals with the drain being the top semiconductor layer,the method comprising: using lithographic resist imaging to defineregions along a top surface of the body layer substrate where the drainlayer to block formation of the drain layer, the drain layer beingformed where said resist has been removed.
 22. The method of claim 21where the drain layer is doped by ion implantation.
 23. The method ofclaim 22 further comprising thermal processing wherein the total lateraldiffusion of dopants in the drain layer is insufficient to invert theentire semiconductor region under the resist while doping the drainlayer by ion implantation.
 24. A method of forming a field effectsemiconductor diode, where the diode comprises semiconductor layers onan upper surface of a substrate and forming a source, a body and a drainof a field effect device, the semiconductor layers being stackedvertically and forming pedestals and the method including: an angled ionimplantation process which implants dopant into the side regions of thepedestals.
 25. The method of claim 24 wherein at some time during theimplantation step, the angle of the path of the ions is greater than 0and less than or equal to 15 degrees when compared to a rayperpendicular to the substrate surface.
 26. The method of claim 24wherein at some time during the implantation step the angle of the pathof the ions is greater than 15 and less than or equal to 30 degrees whencompared to a ray perpendicular to the substrate surface.
 27. The methodof claim 24 wherein at some time during the implantation step, the angleof the path of the ions is greater than 30 and less than or equal to 60degrees when compared to a ray perpendicular to the substrate surface.28. A method of forming a field effect semiconductor diode, where thediode comprises semiconductor layers on an upper surface of a substrateand forming a source, a body and a drain of a field effect device, thesemiconductor layers being stacked vertically and forming pedestals andthe method including: forming a starting substrate surface byepitaxially growing silicon upon a silicon substrate.
 29. The method ofclaim 28 wherein the epitaxially grown silicon is doped to be P-Type.30. A method of forming a field effect semiconductor diode, where thediode comprises semiconductor layers on an upper surface of a substrateand forming a source, a body and a drain of a field effect device, thesemiconductor layers being stacked vertically and forming pedestals andthe method including: forming an electrical contact layer by depositingtitanium metal.
 31. The method of claim 30 further comprising thermallyheating the deposited titanium until it reacts with the underlyingsilicon surfaces.